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lt1806/lt1807 1 the lt ? 1806/lt1807 are single/dual low noise rail-to-rail input and output unity-gain stable op amps that feature a 325mhz gain-bandwidth product, a 140v/ m s slew rate and a 85ma output current. they are optimized for low voltage, high performance signal conditioning systems. the lt1806/lt1807 have a very low distortion of C 80dbc at 5mhz, a low input referred noise voltage of 3.5nv/ ? hz and a maximum offset voltage of 550 m v that allows them to be used in high performance data acquisition systems. the lt1806/lt1807 have an input range that includes both supply rails and an output that swings within 20mv of either supply rail to maximize the signal dynamic range in low supply applications. the lt1806/lt1807 maintain their performance for sup- plies from 2.5v to 12.6v and are specified at 3v, 5v and 5v supplies. the inputs can be driven beyond the sup- plies without damage or phase reversal of the output. the lt1806 is available in an 8-pin so package with the standard op amp pinout and a 6-pin sot-23 package. the lt1807 features the standard dual op amp pinout and is available in 8-pin so and msop packages.these devices can be used as plug-in replacements for many op amps to improve input/output range and performance. , ltc and lt are registered trademarks of linear technology corporation. 325mhz, single/dual, rail-to-rail input and output, low distortion, low noise precision op amps n low voltage, high frequency signal processing n driving a/d converters n rail-to-rail buffer amplifiers n active filters n video line driver gain of 20 differential a/d driver n gain bandwidth product: 325mhz n slew rate: 140v/ m s n wide supply range: 2.5v to 12.6v n large output current: 85ma n low distortion, 5mhz: C80dbc n low voltage noise: 3.5nv/ ? hz n input common mode range includes both rails n output swings rail-to-rail n input offset voltage (rail-to-rail): 550 m v max n common mode rejection: 106db typ n power supply rejection: 105db typ n unity-gain stable n power down pin (lt1806) n single in so-8 and 6-pin sot-23 packages n dual in so-8 and 8-pin msop packages n operating temperature range: C40 c to 85 c features descriptio u applicatio s u typical applicatio u + 1/2 lt1807 r2 909 r5 49.9 r6 49.9 r3 100 v in r1 100 c1 5.6pf c2 5.6pf + 1/2 lt1807 r4 1k c3 470pf ltc 1420 pga gain = 1 v ref = 4.096v 12 bits 10msps +av in 5v ?v 18067 ta01 ?v in frequency (mhz) 0 ?20 amplitude (db) ?00 ?0 ?0 ?0 ?0 0 1234 18067 ta02 5 v s = 5v a v = 20 f sample = 10msps f in = 1.4086mhz sfdr = 83db nonaveraged v in = 200mv p-p 4096 point fft response
lt1806/lt1807 2 total supply voltage (v + to v C ) ............................ 12.6v input voltage (note 2) ............................................. v s input current (note 2) ........................................ 10ma output short-circuit duration (note 3) ............ indefinite operating temperature range (note 4) .. C 40 c to 85 c order part number s6 part marking t jmax = 150 c, q ja = 100 c/w (note 9) ltnk ltnl lt1806cs6 lt1806is6 (note 1) absolute axi u rati gs w ww u specified temperature range (note 5) ... C 40 c to 85 c junction temperature ........................................... 150 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c package/order i for atio uu w order part number s8 part marking 1806 1806i lt1806cs8 lt1806is8 top view nc v + out nc shdn ?n +in v s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 + t jmax = 150 c, q ja = 160 c/w (note 9) out 1 v 2 +in 3 6 v + 5 shdn 4 in top view s6 package 6-lead plastic sot-23 order part number ms8 part marking lttt lttv lt1807cms8 lt1807ims8 order part number s8 part marking 1807 1807i lt1807cs8 LT1807IS8 top view v + out b in b +in b out a ?n a +in a v s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 + + t jmax = 150 c, q ja = 100 c/w (note 9) 1 2 3 4 out a in a +in a v 8 7 6 5 v + out b in b +in b top view ms8 package 8-lead plastic msop t jmax = 150 c, q ja = 135 c/w (note 9) symbol parameter conditions min typ max units v os input offset voltage v cm = v + 100 550 m v v cm = v C 100 550 m v v cm = v + (lt1806 sot-23) 100 700 m v v cm = v C (lt1806 sot-23) 100 700 m v d v os input offset voltage shift v cm = v C to v + 50 550 m v v cm = v C to v + (lt1806 sot-23) 100 700 m v input offset voltage match (channel-to-channel) v cm = v C to v + 200 1000 m v (note 10) i b input bias current v cm = v + 14 m a v cm = v C + 0.2v C13 C 5 m a d i b input bias current shift v cm = v C to v + 617 m a input bias current match (channel-to-channel) v cm = v + 0.03 1.2 m a (note 10) v cm = v C + 0.2v 0.05 3.0 m a t a = 25 c. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. electrical characteristics consult factory for parts specified with wider operating temperature ranges.
lt1806/lt1807 3 symbol parameter conditions min typ max units i os input offset current v cm = v + 0.03 0.6 m a v cm = v C + 0.2v 0.05 1.5 m a d i os input offset current shift v cm = v C + 0.2v to v + 0.08 2.1 m a input noise voltage 0.1hz to 10hz 800 nv p-p e n input noise voltage density f = 10khz 3.5 nv/ ? hz i n input noise current density f = 10khz 1.5 pa/ ? hz c in input capacitance 2pf a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 75 220 v/mv v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 9 22 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 60 150 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + 79 100 db v s = 3v, v cm = v C to v + 74 95 db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + 73 100 db v s = 3v, v cm = v C to v + 68 95 db input common mode range v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v 90 105 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v 84 105 db minimum supply voltage (note 6) 2.3 2.5 v v ol output voltage swing low (note 7) no load 8 50 mv i sink = 5ma 50 130 mv i sink = 25ma 170 375 mv v oh output voltage swing high (note 7) no load 15 65 mv i source = 5ma 85 180 mv i source = 25ma 350 650 mv i sc short-circuit current v s = 5v 35 85 ma v s = 3v 30 65 ma i s supply current per amplifier 913 ma disable supply current v s = 5v, v shdn = 0.3v 0.40 0.9 ma v s = 3v, v shdn = 0.3v 0.22 0.7 ma i shdn shdn pin current v s = 5v, v shdn = 0.3v 150 350 m a v s = 3v, v shdn = 0.3v 100 300 m a shutdown output leakage current v shdn = 0.3v 0.1 75 m a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 w 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 w 50 ns gbw gain bandwidth product frequency = 6mhz 325 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v 125 v/ m s fpbw full power bandwidth v s = 5v, v out = 4v p-p 10 mhz hd harmonic distortion v s = 5v, a v = 1, r l = 1k, v o = 2v p-p , f c = 5mhz C78 dbc t s settling time 0.01%, v s = 5v, v step = 2v, a v = 1, r l = 1k 60 ns d g differential gain (ntsc) v s = 5v, a v = 2, r l = 150 0.015 % dq differential phase (ntsc) v s = 5v, a v = 2, r l = 150 0.05 deg t a = 25 c. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply unless otherwise noted. electrical characteristics
lt1806/lt1807 4 the l denotes the specifications which apply over the 0 c < t a < 70 c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v + l 200 700 m v v cm = v C l 200 700 m v v cm = v + (lt1806 sot-23) l 200 850 m v v cm = v C (lt1806 sot-23) l 200 850 m v v os tc input offset voltage drift (note 8) v cm = v + l 1.5 5 m v/ c v cm = v C l 1.5 5 m v/ c d v os input offset voltage shift v cm = v C to v + l 100 700 m v v cm = v C to v + (lt1806 sot-23) l 100 850 m v input offset voltage match (channel-to-channel) v cm = v C , v cm = v + l 300 1200 m v (note 10) i b input bias current v cm = v + C 0.2v l 15 m a v cm = v C + 0.4v l C15 C5 m a d i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 620 m a input bias current match (channel-to-channel) v cm = v + C 0.2v l 0.03 1.5 m a (note 10) v cm = v C + 0.4v l 0.05 3.5 m a i os input offset current v cm = v + C 0.2v l 0.03 0.75 m a v cm = v C + 0.4v l 0.05 1.80 m a d i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.08 2.55 m a a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 l 60 175 v/mv v s = 5v, v o = 1v to 4v, r l = 100 w to v s /2 l 7.5 20 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 l 45 140 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + l 77 94 db v s = 3v, v cm = v C to v + l 72 89 db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + l 71 94 db v s = 3v, v cm = v C to v + l 66 89 db input common mode range l v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 88 105 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v l 82 105 db minimum supply voltage (note 6) v cm = v o = 0.5v l 2.3 2.5 v v ol output voltage swing low (note 7) no load l 12 60 mv i sink = 5ma l 60 140 mv i sink = 25ma l 180 425 mv v oh output voltage swing high (note 7) no load l 30 120 mv i source = 5ma l 110 220 mv i source = 25ma l 360 700 mv i sc short-circuit current v s = 5v l 30 65 ma v s = 3v l 25 55 ma i s supply current per amplifier l 10 14 ma disable supply current v s = 5v, v shdn = 0.3v l 0.40 1.1 ma v s = 3v, v shdn = 0.3v l 0.22 0.9 ma i shdn shdn pin current v s = 5v, v shdn = 0.3v l 160 400 m a v s = 3v, v shdn = 0.3v l 110 350 m a shutdown output leakage current v shdn = 0.3v l 1 m a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 w l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 w l 50 ns gbw gain bandwidth product frequency = 6mhz l 300 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v l 100 v/ m s fpbw full power bandwidth v s = 5v, v o = 4v p-p l 8 mhz
lt1806/lt1807 5 symbol parameter conditions min typ max units v os input offset voltage v cm = v + l 200 800 m v v cm = v C l 200 800 m v v cm = v + (lt1806 sot-23) l 200 950 m v v cm = v C (lt1806 sot-23) l 200 950 m v v os tc input offset voltage drift (note 8) v cm = v + l 1.5 5 m v/ c v cm = v C l 1.5 5 m v/ c d v os input offset voltage shift v cm = v C l 100 800 m v v cm = v C to v + (lt1806 sot-23) l 100 950 m v input offset voltage match (channel-to-channel) v cm = v + , v cm = v C l 200 1400 m v (note 10) i b input bias current v cm = v + C 0.2v l 16 m a v cm = v C + 0.4v l C16 C5 m a d i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 622 m a input bias current match (channel-to-channel) v cm = v + C 0.2v l 0.02 1.8 m a (note 10) v cm = v C + 0.4v l 0.05 4.0 m a i os input offset current v cm = v + C 0.2v l 0.02 0.9 m a v cm = v C + 0.4v l 0.05 2.1 m a d i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.07 3 m a a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 l 50 140 v/mv v s = 5v, v o = 1v to 4v, r l = 100 w to v s /2 l 616 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 l 35 100 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + l 75 94 db v s = 3v, v cm = v C to v + l 71 89 db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + l 69 94 db v s = 3v, v cm = v C to v + l 65 89 db input common mode range l v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 86 105 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v l 80 105 db minimum supply voltage (note 6) v cm = v o = 0.5v l 2.3 2.5 v v ol output voltage swing low (note 7) no load l 15 70 mv i sink = 5ma l 65 150 mv i sink = 20ma l 170 400 mv v oh output voltage swing high (note 7) no load l 30 130 mv i source = 5ma l 110 240 mv i source = 20ma l 350 700 mv i sc short-circuit current v s = 5v l 22 45 ma v s = 3v l 20 40 ma i s supply current per amplifier l 11 16 ma disable supply current v s = 5v, v shdn = 0.3.v l 0.4 1.2 ma v s = 3v, v shdn = 0.3v l 0.3 1.0 ma i shdn shdn pin current v s = 5v, v shdn = 0.3v l 170 450 m a v s = 3v, v shdn = 0.3v l 120 400 m a shutdown output leakage current v shdn = 0.3v l 1.2 m a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 w l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 w l 50 ns gbw gain bandwidth product frequency = 6mhz l 250 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v l 80 v/ m v fpbw full power bandwidth v s = 5v, v o = 4v p-p l 6 mhz the l denotes the specifications which apply over the C 40 c < t a < 85 c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. (note 5) electrical characteristics
lt1806/lt1807 6 symbol parameter conditions min typ max units v os input offset voltage v cm = v + 100 700 m v v cm = v C 100 700 m v v cm = v + (lt1806 sot-23) 100 750 m v v cm = v C (lt1806 sot-23) 100 750 m v d v os input offset voltage shift v cm = v C to v + 50 700 m v v cm = v C to v + (lt1806 sot-23) 50 750 m v input offset voltage match (channel-to-channel) v cm = v C , v cm = v + 200 1200 m v (note 10) i b input bias current v cm = v + 15 m a v cm = v C + 0.2v C14 C5 m a d i b input bias current shift v cm = v C + 0.2v to v + 619 m a input bias current match (channel-to-channel) v cm = v + 0.03 1.4 m a (note 10) v cm = v C + 0.2v 0.05 3.2 m a i os input offset current v cm = v + 0.03 0.7 m a v cm = v C + 0.2v 0.04 1.6 m a d i os input offset current shift v cm = v C + 0.2v to v + 0.07 2.3 m a input noise voltage 0.1hz to 10hz 800 nv p-p e n input noise voltage density f = 10khz 3.5 nv/ ? hz i n input noise current density f = 10khz 1.5 pa/ ? hz c in input capacitance f = 100khz 2 pf a vol large-signal voltage gain v o = C4v to 4v, r l = 1k 100 300 v/mv v o = C2.5v to 2.5v, r l = 100 w 10 27 v/mv cmrr common mode rejection ratio v cm = v C to v + 83 106 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + 77 106 db input common mode range v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v 90 105 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v 84 105 db v ol output voltage swing low (note 7) no load 14 60 mv i sink = 5ma 55 140 mv i sink = 25ma 180 450 mv v oh output voltage swing high (note 7) no load 20 70 mv i source = 5ma 90 200 mv i source = 25ma 360 700 mv i sc short-circuit current 40 85 ma i s supply current per amplifier 11 16 ma disable supply current v shdn = 0.3v 0.4 1.2 ma i shdn shdn pin current v shdn = 0.3v 150 350 m a shutdown output leakage current v shdn = 0.3v 0.3 75 m a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 w 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 w 50 ns gbw gain bandwidth product frequency = 6mhz 170 325 mhz sr slew rate a v = C1, r l = 1k , v o = 4v, measured at v o = 3v 70 140 v/ m s fpbw full power bandwidth v o = 8v p-p 5.5 mhz hd harmonic distortion a v = 1, r l = 1k, v o = 2v p-p , f c = 5mhz C80 dbc t s settling time 0.01%, v step = 8v, a v = 1, r l = 1k 120 ns d g differential gain (ntsc) a v = 2, r l = 150 0.01 % dq differential phase (ntsc) a v = 2, r l = 150 0.01 deg t a = 25 c. v s = 5v, v shdn = open; v cm = 0v, v out = 0v, unless otherwise noted. electrical characteristics
lt1806/lt1807 7 the l denotes specifications which apply over the 0 c < t a < 70 c temperature range. v s = 5v, v shdn = open; v cm = 0v, v out = 0v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + l 200 800 m v v cm = v C l 200 800 m v v cm = v + (lt1806 sot-23) l 200 900 m v v cm = v C (lt1806 sot-23) l 200 900 m v v os tc input offset voltage drift (note 8) v cm = v + l 1.5 5 m v/ c v cm = v C l 1.5 5 m v/ c d v os input offset voltage shift v cm = v C to v + l 100 800 m v v cm = v C to v + (lt1806 sot-23) l 100 900 m v input offset voltage match (channel-to channel) v cm = v C , v cm = v + l 300 1400 m v (note 10) i b input bias current v cm = v + C 0.2v l 16 m a v cm = v C + 0.4v l C15 C 6 m a d i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 721 m a input bias current match (channel-to-channel) v cm = v + C 0.2v l 0.03 1.8 m a (note 10) v cm = v C + 0.4v l 0.04 3.8 m a i os input offset current v cm = v + C 0.2v l 0.03 0.9 m a v cm = v C + 0.4v l 0.04 1.9 m a d i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.07 2.8 m a a vol large-signal voltage gain v o = C4v to 4v, r l = 1k l 80 250 v/mv v o = C2.5v to 2.5v, r l = 100 w l 825 v/mv cmrr common mode rejection ratio v cm = v C to v + l 81 100 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + l 75 100 db input common mode range l v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v l 88 105 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v l 82 106 db v ol output voltage swing low (note 7) no load l 18 80 mv i sink = 5ma l 60 160 mv i sink = 25ma l 185 500 mv v oh output voltage swing high (note 7) no load l 40 140 mv i source = 5ma l 110 240 mv i source = 25ma l 360 750 mv i sc short-circuit current l 35 75 ma i s supply current per amplifier l 14 20 ma disable supply current v shdn = 0.3v l 0.4 1.4 ma i shdn shdn pin current v shdn = 0.3v l 160 400 m a shutdown output leakage current v shdn = 0.3v l 1 m a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 w l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 w l 50 ns gbw gain bandwidth product frequency = 6mhz l 150 300 mhz sr slew rate a v = C1, r l = 1k , v o = 4v, l 60 120 v/ m s measure at v o = 3v fpbw full power bandwidth v o = 8v p-p l 4.5 mhz electrical characteristics
lt1806/lt1807 8 symbol parameter conditions min typ max units v os input offset voltage v cm = v + l 200 900 m v v cm = v C l 200 900 m v v cm = v + (lt1806 sot-23) l 200 975 m v v cm = v C (lt1806 sot-23) l 200 975 m v v os tc input offset voltage drift (note 8) v cm = v + l 1.5 5 m v/ c v cm = v C l 1.5 5 m v/ c d v os input offset voltage shift v cm = v C to v + l 100 900 m v v cm = v C to v + (lt1806 sot-23) l 100 975 m v input offset voltage match (channel-to-channel) v cm = v C to v + l 300 1600 m v (note 10) i b input bias current v cm = v + C 0.2v l 1.2 7 m a v cm = v C + 0.4v l C16 C 5 m a d i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 623 m a input bias current match (channel-to-channel) v cm = v + C 0.2v l 0.03 2.0 m a (note 10) v cm = v C + 0.4v l 0.04 4.5 m a i os input offset current v cm = v + C 0.2v l 0.03 1.0 m a v cm = v C + 0.4v l 0.04 2.2 m a d i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.07 3.2 m a a vol large-signal voltage gain v o = C4v to 4v, r l = 1k l 60 175 v/mv v o = C2v to 2v, r l =100 w l 717 v/mv cmrr common mode rejection ratio v cm = v C to v + l 80 100 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + l 74 100 db input common mode range l v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v l 86 105 db psrr match (channel-to-channel) (note 10) l 80 105 db v ol output voltage swing low (note 7) no load l 20 100 mv i sink = 5ma l 65 170 mv i sink = 20ma l 200 500 mv v oh output voltage swing high (note 7) no load l 50 160 mv i source = 5ma l 115 260 mv i source = 20ma l 360 700 mv i sc short-circuit current l 25 55 ma i s supply current l 15 22 ma disable supply current v shdn = 0.3v l 0.45 1.5 ma i shdn shdn pin current v shdn = 0.3v l 170 450 m a shutdown output leakage current v shdn = 0.3v l 1.2 m a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 w l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 w l 50 ns gbw gain bandwidth product frequency = 6mhz l 125 290 mhz sr slew rate a v = C1, r l = 1k , v o = 4v, l 50 100 v/ m s measured at v o = 3v fpbw full power bandwidth v o = 8v p-p l 4 mhz the l denotes the specifications which apply over the C40 c < t a < 85 c temperature range. v s = 5v, v shdn = open; v cm = 0v, v out = 0v, unless otherwise noted. (note 5) electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: the inputs are protected by back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma.
lt1806/lt1807 9 note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. note 4: the lt1806c/lt1806i and lt1807c/lt1807i are guaranteed functional over the temperature range of C40 c and 85 c. note 5: the lt1806c/lt1807c are guaranteed to meet specified performance from 0 c to 70 c. the lt1806c/lt1807c are designed, characterized and expected to meet specified performance from C40 c to 85 c but are not tested or qa sampled at these temperatures. the lt1806i/lt1807i are guaranteed to meet specified performance from C40 c to 85 c. note 6: minimum supply voltage is guaranteed by power supply rejection ratio test. note 7: output voltage swings are measured between the output and power supply rails. note 8: this parameter is not 100% tested. note 9: thermal resistance varies depending upon the amount of pc board metal attached to the v C pin of the device. q ja is specified for a certain amount of 2oz copper metal trace connecting to the v C pin as described in the thermal resistance tables in the applications information section. note 10: matching parameters are the difference between the two amplifiers of the lt1807. electrical characteristics typical perfor a ce characteristics uw v os distribution, v cm = 0v (pnp stage) input offset voltage ( v) 500 percent of units (%) 30 40 50 300 18067 g01 20 10 0 300 ?00 100 500 v s = 5v, 0v v cm = 0v input offset voltage ( v) 500 percent of units (%) 30 40 50 300 18067 g02 20 10 0 300 ?00 100 500 v s = 5v, 0v v cm = 5v input offset voltage ( v) 500 percent of units (%) 30 40 50 300 18067 g03 20 10 0 300 ?00 100 500 v s = 5v, 0v v os distribution, v cm = 5v (npn stage) d v os shift for v cm = 0v to 5v supply current per amp vs supply voltage offset voltage vs input common mode input bias current vs common mode voltage common mode voltage (v) ? ?0 input bias current ( a) ? 0 5 0123 18067 g06 456 t a = 125 c t a = 25 c t a = 55 c v s = 5v, 0v t a = 125 c t a = 25 c t a = 55 c total supply voltage (v) 0 supply current (ma) 12 18067 g04 345 2 1 678 91011 20 15 10 5 0 t a = 125 c t a = 25 c t a = 55 c input common mode voltage (v) 0 offset voltage ( v) 100 300 500 4 18067 g05 ?00 300 0 200 400 200 400 500 1 2 3 5 t a = 125 c t a = 55 c t a = 25 c v s = 5v, 0v typical part
lt1806/lt1807 10 typical perfor a ce characteristics uw input bias current vs temperature output saturation voltage vs load current (output low) temperature ( c) ?0 ? input bias ( a) ? ? ? ? 2 ? ?0 10 25 85 18067 g07 ? 0 1 ? ?5 5 40 55 70 npn active v s = 5v, 0v v cm = 5v pnp active v s = 5v, 0v v cm = 0v output saturation voltage vs load current (output high) load current (ma) 0.01 0.001 output saturation voltage (v) 0.1 10 1 100 0.1 10 18067 g09 0.01 1 t a = 125 c t a = 55 c t a = 25 c v s = 5v minimum supply voltage output short-circuit current vs power supply voltage supply current vs shdn pin voltage total supply voltage (v) 1.0 ?.0 change in offset voltage (mv) 0.8 0.4 0.2 0 1.0 0.4 2.0 3.0 3.5 18067 g10 0.6 0.6 0.8 0.2 1.5 2.5 4.0 4.5 5.0 t a = 125 c t a = 55 c t a = 25 c shdn pin voltage (v) 0 0 supply current (ma) 2 6 8 10 2 4 5 18 18067 g12 4 13 12 14 16 t a = 125 c t a = 55 c t a = 25 c v s = 5v, 0v shdn pin current vs shdn pin voltage shdn pin voltage (v) 0 shdn pin current ( a) ?0 ?0 20 4 18067 g13 ?00 ?40 ?0 ?0 0 ?20 ?60 ?80 1 2 3 5 t a = 125 c t a = 55 c t a = 25 c v s = 5v, 0v open-loop gain output voltage (v) 0 500 input voltage ( v) 300 ?00 100 0.5 1.0 1.5 2.0 18067 g14 2.5 300 500 400 200 0 200 400 3.0 r l = 1k r l = 100 v s = 3v, 0v r l to gnd open-loop gain output voltage (v) 0 500 input voltage ( v) 300 ?00 100 0.5 1.0 1.5 2.0 18067 g15 2.5 300 500 400 200 0 200 400 3.0 3.5 4.0 4.5 5.0 r l = 1k r l = 100 v s = 5v, 0v r l to gnd power supply voltage ( v) 1.5 output short-circuit current (ma) ?0 80 100 120 2.5 3.5 4.0 18067 g11 ?0 40 0 ?0 60 ?00 20 ?0 2.0 3.0 4.5 5.0 t a = 55 c t a = 55 c t a = 125 c t a = 25 c ?inking ?ourcing t a = 125 c t a = 25 c load current (ma) 0.01 0.001 output saturation voltage (v) 0.1 10 0.1 1 10 100 18067 g08 0.01 1 v s = 5v t a = 125 c t a = 25 c t a = 55 c
lt1806/lt1807 11 typical perfor a ce characteristics uw open-loop gain output voltage (v) ? 500 input voltage ( v) 300 ?00 100 ? ? ? 1 18067 g16 0 300 500 400 200 0 200 400 12345 r l = 1k r l = 100 v s = 5v output current (ma) ?00 2.5 offset voltage (mv) ?.5 0.5 0.5 ?0 ?0 ?0 20 18067 g17 0 1.5 2.5 2.0 ?.0 0 1.0 2.0 20 40 60 80 100 t a = 125 c t a = 55 c t a = 25 c v s = 5v offset voltage vs output current time after power-up (sec) 0 offset voltage drift ( v) 25 30 35 160 140 120 100 80 18067 g18 20 15 0 20 40 60 10 5 45 40 v s = 5v v s = 2.5v v s = 1.5v warm-up drift vs time (lt1806s8) input noise voltage vs frequency input noise current vs frequency 0.1hz to 10hz output voltage noise time (sec) 0 output voltage (nv) 200 600 1000 8 18067 g21 200 600 0 400 800 400 800 ?000 2 1 4 3 67 9 5 10 gain bandwidth and phase margin vs supply voltage total supply voltage (v) 0 gain bandwidth (mhz) phase margin (deg) 8 18067 g22 400 300 350 250 200 35 45 55 30 40 50 2 1 4 3 67 9 5 10 t a = 25 c phase margin gain bandwidth product gain bandwidth and phase margin vs temperature temperature ( c) ?5 gain bandwidth (mhz) phase margin (deg) 105 18067 g23 400 300 350 250 200 35 45 55 30 40 50 ?5 ?5 25 5 65 85 125 45 phase margin v s = 5v phase margin v s = 3v gbw product v s = 5v gbw product v s = 3v temperature ( c) ?5 75 slew rate ( v/ s) 100 125 150 175 35 ?5 5 25 18067 g24 45 65 85 105 125 a v = ? r f = r g = 1k r l = 1k v s = 5v v s = 2.5v slew rate vs temperature frequency (khz) 0.1 0 8 10 12 1 10 100 18067 g19 6 4 2 noise voltage (nv/ hz) v s = 5v, 0v npn active v cm = 4.5v pnp active v cm = 2.5v frequency (khz) 0.1 0 8 10 12 1 10 100 18067 g19 6 4 2 noise current (pa/ hz) v s = 5v, 0v npn active v cm = 4.5v pnp active v cm = 2.5v
lt1806/lt1807 12 typical perfor a ce characteristics uw gain and phase vs frequency gain vs frequency (a v = 1) gain vs frequency (a v = 2) frequency (mhz) 20 gain (db) phase (deg) 40 50 70 0.1 10 100 500 18067 g25 0 1 60 30 10 ?0 ?0 ?0 ?5 45 90 180 225 ?35 135 0 ?0 180 225 phase v s = 5v gain v s = 5v gain v s = 3v phase v s = 3v c l = 5pf r l = 100 output impedance vs frequency common mode rejection ratio vs frequency power supply rejection ratio vs frequency frequency (mhz) 0.01 40 common mode rejection ratio (db) 50 60 70 80 0.1 1 10 100 500 18067 g29 30 20 10 0 90 100 v s = 5v, 0v frequency (mhz) 0.001 40 power supply rejection ratio (db) 50 60 70 80 0.01 0.1 1 10 100 18067 g30 30 20 10 0 90 100 v s = 5v, 0v t a = 25 c negative supply positive supply series output resistor vs capacitive load capacitive load (pf) 10 0 overshoot (%) 10 20 30 40 100 1000 18067 g31 50 5 15 25 35 45 v s = 5v, 0v a v = 1 r os = 10 r os = 20 r os = r l = 50 series output resistor vs capacitive load capacitive load (pf) 10 0 overshoot (%) 10 20 30 40 100 1000 18067 g32 50 5 15 25 35 45 v s = 5v, 0v a v = 2 r os = 10 r os = 20 r os = r l = 50 0.01% settling time frequency (mhz) 0 gain (db) 12 18 30 0.1 10 100 500 18067 g26 ?2 1 24 6 ? ?8 ?4 ?6 c l = 10pf r l = 100 v s = 3v v s = 5v frequency (mhz) 6 gain (db) 12 15 21 0.1 10 100 500 18067 g27 0 1 18 9 3 ? ? ? c l = 10pf r l = 100 v s = 5v v s = 3v frequency (hz) 100k 0.001 output impedance ( ) 0.01 0.1 1 10 100 600 1m 10m 100m 500m 18067 g28 v s = 5v, 0v a v = 10 a v = 2 a v = 1 input signal generation (2v/div) output settling resolution (2mv/div) v s = 5v 20ns/div 18067 g33 v out = 4v rl = 500 w t s = 120ns (settling time)
lt1806/lt1807 13 typical perfor a ce characteristics uw frequency (mhz) 0.3 ?0 distortion (dbc) ?0 ?0 ?0 11030 18067 g34 ?0 ?0 ?00 ?10 a v = 1 v out = 2v p-p v s = 5v r l = 100 , 2nd r l = 100 , 3rd r l = 1k, 3rd r l = 1k, 2nd distortion vs frequency frequency (mhz) 0.3 ?0 distortion (dbc) ?0 ?0 ?0 11030 18067 g35 ?0 ?0 ?00 ?10 a v = 1 v out = 2v p-p v s = 5v, 0v r l = 100 , 2nd r l = 100 , 3rd r l = 1k, 3rd r l = 1k, 2nd distortion vs frequency distortion vs frequency maximum undistorted output signal vs frequency distortion vs frequency 5v large-signal response 5v small-signal response 5v large-signal response v s = 5v 40ns/div 18067 g39 freq = 1.92mhz a v = 1 r l = 1k v s = 5v 20ns/div 18067 g40 freq = 4.48mhz a v = 1 r l = 1k v s = 5v, 0v 20ns/div 18067 g41 freq = 5.29mhz a v = 1 r l = 1k frequency (mhz) 0.3 ?0 distortion (dbc) ?0 ?0 ?0 11030 18067 g36 ?0 ?0 ?00 ?20 ?10 a v = 2 v out = 2v p-p v s = 5v r l = 100 , 2nd r l = 100 , 3rd r l = 1k, 3rd r l = 1k, 2nd frequency (mhz) 0.3 ?0 distortion (dbc) ?0 ?0 ?0 11030 18067 g37 ?0 ?0 ?00 ?20 ?10 a v = 2 v out = 2v p-p v s = 5v, 0v r l = 100 , 2nd r l = 100 , 3rd r l = 1k, 3rd r l = 1k, 2nd frequency (mhz) 0.1 4.3 output voltage swing (v p-p ) 4.4 4.5 4.6 1 10 100 18067 g38 4.2 4.1 4.0 3.9 v s = 5v, 0v a v = ? a v = +2 0v 0v 0.5v
lt1806/lt1807 14 5v small-signal response output overdriven recovery shutdown response v s = 5v, 0v 10ns/div 18067 g42 a v = 1 r l = 1k v s = 5v, 0v 100ns/div 18067 g43 a v = 2 r l = 1k v s = 5v, 0v 200ns/div 18067 g44 a v = 2 r l = 100 w typical perfor a ce characteristics uw v in (1v/div) v out (2v/div) v shdn (2v/div) 0v v out (2v/div) 0v applicatio s i for atio wu uu rail-to-rail characteristics the lt1806/lt1807 have input and output signal range that covers from negative power supply to positive power supply. figure 1 depicts a simplified schematic of the amplifier. the input stage is comprised of two differential amplifiers, a pnp stage q1/q2 and a npn stage q3/q4 that are active over different ranges of common mode input voltage. the pnp differential pair is active between the negative supply to approximately 1.5v below the positive supply. as the input voltage moves closer toward the positive supply, the transistor q5 will steer the tail current i 1 to the current mirror q6/q7, activating the npn differ- ential pair. the pnp pair becomes inactive for the rest of the input common mode range up to the positive supply. a pair of complementary common emitter stages q14/ q15 that enable the output to swing from rail to rail constructs the output stage. the capacitors c1 and c2 form the local feedback loops that lower the output q4 q6 q3 q7 q10 q1 q13 q15 out q2 q11 q12 q9 q5 v bias i 1 d2 d1 d5 d4 d3 d6 d7 d8 esdd2 esdd1 +in ?n v esdd3 esdd4 v + v + v q8 r2 r1 r3 r4 r5 q14 18067 f01 + i 2 c2 c c v + c1 buffer and output bias q17 q16 esdd5 shdn v + v r7 100k r6 40k d9 v + v esdd6 bias generation figure 1. lt1806 simplified schematic diagram 0v 0v 0v
lt1806/lt1807 15 applicatio s i for atio wu uu imped ance at high frequency. these devices are fabri- cated on linear technologys proprietary high speed complementary bipolar process. power dissipation the lt1806/lt1807 amplifiers combine high speed with large output current in a small package, so there is a need to ensure that the dies junction temperature does not exceed 150 c. the lt1806 is housed in an so-8 package or a 6-lead sot-23 package and the lt1807 is in an so-8 or 8-lead msop package. all packages have the v C supply pin fused to the lead frame to enhance the thermal conduc- tance when connecting to a ground plane or a large metal trace. metal trace and plated through-holes can be used to spread the heat generated by the device to the backside of the pc board. for example, on a 3/32" fr-4 board with 2oz copper, a total of 660 square millimeters connects to pin 4 of lt1807 in an so-8 package (330 square millimeters on each side of the pc board) will bring the thermal resis- tance, q ja , to about 85 c/w. without extra metal trace beside the power line connecting to the v C pin to provide a heat sink, the thermal resistance will be around 105 c/w. more information on thermal resistance for all packages with various metal areas connecting to the v C pin is provided in tables 1, 2 and 3. table 1. lt1806 6-lead sot-23 package copper area board area thermal resistance topside (mm 2 ) (mm 2 ) (junction-to-ambient) 270 2500 135 c/w 100 2500 145 c/w 20 2500 160 c/w 0 2500 200 c/w device is mounted on topside. table 2. lt1806/lt1807 so-8 package copper area topside backside board area thermal resistance (mm 2 ) (mm 2 ) (mm 2 ) (junction-to-ambient) 1100 1100 2500 65 c/w 330 330 2500 85 c/w 35 35 2500 95 c/w 35 0 2500 100 c/w 0 0 2500 105 c/w device is mounted on topside. table 3. lt1807 8-lead msop package copper area topside backside board area thermal resistance (mm 2 ) (mm 2 ) (mm 2 ) (junction-to-ambient) 540 540 2500 110 c/w 100 100 2500 120 c/w 100 0 2500 130 c/w 30 0 2500 135 c/w 0 0 2500 140 c/w device is mounted on topside. junction temperature t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j = t a + (p d ? q ja ) the power dissipation in the ic is the function of the supply voltage, output voltage and the load resistance. for a given supply voltage, the worst-case power dissipation p d(max) occurs at the maximum quiescent supply current and at the output voltage which is half of either supply voltage (or the maximum swing if it is less than 1/2 the supply voltage). p d(max) is given by: p d(max) = (v s ? i s(max) ) + (v s /2) 2 /r l example: an lt1807 in so-8 mounted on a 2500mm 2 area of pc board without any extra heat spreading plane connected to its v C pin has a thermal resistance of 105 c/w, q ja . operating on 5v supplies with both amplifiers simultaneously driving 50 w loads, the worst- case power dissipation is given by: p d(max) = 2 ? (10 ? 14ma) + 2 ? (2.5) 2 /50 = 0.28 + 0.25 = 0.53w the maximum ambient temperature that the part is allowed to operate is: t a = t j C (p d(max) ? 105 c/w) = 150 c C (0.53w ? 105 c/w) = 94 c to operate the device at higher ambient temperature, connect more metal area to the v C pin to reduce the thermal resistance of the package as indicated in table 2.
lt1806/lt1807 16 input offset voltage the offset voltage will change depending upon which input stage is active and the maximum offset voltage is guaran- teed to less than 550 m v. to maintain the precision charac- teristics of the amplifier, the change of v os over the entire input common mode range (cmrr) is limited to be less than 550 m v on a single 5v and 3v supply. input bias current the input bias current polarity depends on a given input common voltage at which the input stage is operating. when the pnp input stage is active, the input bias currents flow out of the input pins. when the npn input stage is activated, the input bias current flows into the input pins. because the input offset current is less than the input bias current, matching the source resistances at the input pins will reduce total offset error. output the lt1806/lt1807 can deliver a large output current, so the short-circuit current limit is set around 90ma to prevent damage to the device. attention must be paid to keep the junction temperature of the ic below the absolute maximum rating of 150 c (refer to the power dissipation section) when the output is continuously short-circuited. the output of the amplifier has reverse-biased diodes connected to each supply. if the output is forced beyond either supply, unlimited current will flow through these diodes. if the current is transient and limited to one hundred milliamps or less, no damage to the device will occur. overdrive protection when the input voltage exceeds the power supplies, two pairs of crossing diodes d1 to d4 will prevent the output from reversing polarity. if the input voltage exceeds either power supply by 700mv, diode d1/d2 or d3/d4 will turn on to keep the output at the proper polarity. for the phase reversal protection to perform properly, the input current must be limited to less than 5ma. if the amplifier is severely overdriven, an external resistor should be used to limit the overdrive current. the lt1806/lt1807s input stages are also protected against large differential input voltages of 1.4v or higher by a pair of back-to-back diodes, d5/d8, that prevent the emitter-base breakdown of the input transistors. the current in these diodes should be limited to less than 10ma when they are active. the worst-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity gain configura- tion. in addition, the amplifier is protected against esd strikes up to 3kv on all pins by a pair of protection diodes, esdd1 to esdd6, on each pin that are connected to the power supplies as shown in figure 1. capacitive load the lt1806/lt1807 are optimized for high bandwidth and low distortion applications. they can drive a capacitive load of about 20pf in a unity-gain configuration, and more for higher gain. when driving a larger capacitive load, a resistor of 10 w to 50 w should be connected between the output and the capacitive load to avoid ringing or oscilla- tion. the feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. graphs on capacitive loads indicate the transient response of the amplifier when driving the capacitive load with a specified series resistor. feedback components when feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. for instance, the lt1806/ lt1807 in a noninverting gain of 2, set up with two 1k resistors and a capacitance of 3pf (part plus pc board) will probably ring in transient response. the pole is formed at 106mhz that will reduce phase margin by 34 degrees when the crossover frequency of the amplifier is around 70mhz. a capacitor of 3pf or higher connected across the feedback resistor will eliminate any ringing or oscillation. applicatio s i for atio wu uu
lt1806/lt1807 17 typical applicatio s u driving a/d converter the lt1806/lt1807 have 60ns settling time to 0.01% on a 2v step signal, and 20 w output impedance at 100mhz, that makes them ideal for driving high speed a/d convert- ers. with the rail-to-rail input and output, and low supply voltage operation, the lt1806/lt1807 are also desirable for single supply applications. as shown in the application on the front page of this data sheet, the lt1807 drives a 10msps, 12-bit, ltc1420 adc in a gain of 20. driving the ltc1420 differentially will optimize the signal-to-noise ratio, snr, and the total harmonic distortion, thd, of the a/d converter. the lowpass filter, r5, r6 and c3 reduce noise or distortion products that might come from the input signal. high quality capacitors and resistors, npo chip capacitor and metal film surface mount resistors, should be used since these components can add to distortion. the voltage glitch of the converter, due to its sampling nature is buffered by the lt1807, and the ability of the amplifier to settle it quickly will affect the spurious free dynamic range of the system. figure 2 depicts the lt1806 driving ltc1420 at noninverting gain of 2 con- figuration. the fft responses show a better than 92db of spurious free dynamic range, sfdr. + lt1806 ltc1420 pga gain = 1 ref = 2.048v 5v 5v 12 bits 10msps ?v ?v r2 1k r1 1k v in 1.5v p-p c1 470pf ? in 18067 f02 +a in r3 49.9 figure 2. noninverting a/d driver frequency (mhz) 0 ?20 amplitude (db) ?00 ?0 ?0 ?0 ?0 0 1234 18067 f03 5 v s = 5v a v = 2 f sample = 10msps f in = 1.4086mhz sfdr = 92.5db figure 3. 4096 point fft response shdn pin the lt1806 has a shdn pin to reduce the supply current to less than 0.9ma. when the shdn pin is pulled low, it will generate a signal to power down the device. if the pin is left unconnected, an internal pull-up resistor of 40k will keep the part fully operating as shown in figure 1. the output will be high impedance during shutdown, and the turn-on and turn-off time is less than 100ns. because the input is protected by a pair of back to back diodes, the input signal will feed through to the output during shutdown mode if the amplitude of signal between the inputs is larger than 1.4v. applicatio s i for atio wu uu
lt1806/lt1807 18 typical applicatio s u single supply video line driver the lt1806/lt1807 are wideband rail-to-rail op amps with large output current that allows them to drive video signals in low supply applications. figure 4 depicts a single supply video line driver with ac coupling to mini- mize the quiescent power dissipation. resistors r1 and r2 are used to level-shift the input and output to provide the largest signal swing. the gain of 2 is set up with r3 and r4 to restore the signal at v out , which is attenuated by 6db due to the matching of the 75 w line with the back-terminated resistor, r5. the back termination will eliminate any reflection of the signal that comes from the load. the input termination resistor, r t , is optionalit is used only if matching of the incoming line is necessary. the values of c1, c2 and c3 are selected to minimize the droop of the luminance signal. in some less stringent requirements, the value of capacitors could be reduced. the C 3db bandwidth of the driver is about 90mhz on 5v supply, and the amount of peaking will vary upon the value of capacitor c4. + lt1806 v in 18067 f04 c1 33 f c2 150 f r t 75 r load 75 v out r2 5k r3 1k r4 1k c4 3pf r1 5k 5v 2 3 6 7 4 r5 75 75 coax cable c3 1000 f + + + figure 4. 5v single supply video line driver frequency (mhz) ? voltage gain (db) 4 5 ? ? 3 0 2 1 ? 0.2 10 100 18067 f05 ? 1 v s = 5v, 0v figure 5. video line driver frequency response
lt1806/lt1807 19 typical applicatio s u single 3v supply, 4mhz, 4 th order butterworth filter benefiting from a low voltage supply operation, low distor- tion and rail-to-rail output of lt1806/lt1807, a low dis- tortion filter that is suitable for antialiasing can be built as shown in figure 6. on a 3v supply, the filter built with lt1807 has a passband of 4mhz with 2.5v p-p signal and stopband that is greater than 70db to frequency of 100mhz. as an option to minimize the dc offset voltage at the output, connect a series resistor of 365 w and a bypass capacitor at the noninverting inputs of the amplifiers as shown in figure 6. + v s 2 47pf 1/2 lt1807 220pf 665 v in v out 18067 f06 365 (optional) 232 232 4.7 f (optional) + 22pf 470pf 562 274 274 1/2 lt1807 figure 6. single 3v supply, 4mhz, 4th order butterworth filter figure 7. filter frequency response frequency (hz) 10k 100k 1m 10m 100m gain (db) 18067 f07 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 v s = 3v, 0v v in = 2.5v p-p
lt1806/lt1807 20 1mhz series resonant crystal oscillator with square and sinusoid outputs figure 8 shows a classic 1mhz series resonant crystal oscillator. at series resonance, the crystal is a low imped- ance and the positive feedback connection is what brings about oscillation at the series resonance frequency. the rc feedback around the other path ensures that the circuit does not find a stable dc operating point and refuse to oscillate. the comparator output is a 1mhz square wave with a measured jitter of 28ps rms with a 5v supply and 40ps rms with a 3v supply. on the other side of the crystal, however, is an excellent looking sine wave except for the fact of the small high frequency glitch caused by the fast typical applicatio s u edge and the crystal capacitance (middle trace of fig- ure 9). sinusoid amplitude stability is maintained by the fact that the sine wave is basically a filtered version of the square wave; the usual amplitude control loops associ- ated with sinusoidal oscillators are not immediately nec- essary. 1 one can make use of this sine wave by buffering and filtering it, and this is the combined task of the lt1806. it is configured as a bandpass filter with a q of 5 and does a good job of cleaning up and buffering the sine wave. distortion was measured at C70dbc and C 60dbc on the second and third harmonics. 1 amplitude will be a linear function of comparator output swing, which is supply dependent and therefore controllable. the important difference here is that any added amplitude stabilization loop will not be faced with the classical task of avoiding regions of nonoscillation versus clipping. + 8 square wave v s v s v s 1 7 4 5 r3 1k r4 210 r1 1k r8 2k r9 2k r5 6.49k 1k r7 15.8k r2 1k 1mhz at-cut c1 0.1 f 6 3 2 c2 0.1 f c4 100pf c3 100pf lt1713 + v s 7 6 1 (nc) 4 18067 f08 v s = 2.7v to 6v 3 2 lt1806 le r6 162 100pf sine wave figure 8. lt1713 comparator is configured as a series resonant crystal oscillator. the lt1806 op amp is configured in a q = 5 bandpass filter with f c = 1mhz 3v/div 1v/div 1v/div 200ns/div 1806 f09 figure 9. oscillator waveforms with v s = 3v. top trace is comparator output. middle trace is crystal feedback to pin 2 at lt1713. bottom trace is buffered, inverted and bandpass filtered with a q of 5 by the lt1806
lt1806/lt1807 21 dimensions in inches (millimeters) unless otherwise noted. u package descriptio s6 package 6-lead plastic sot-23 (ltc dwg # 05-08-1634) 1.50 ?1.75 (0.059 ?0.069) 0.35 ?0.55 (0.014 ?0.022) 0.35 ?0.50 (0.014 ?0.020) six places (note 2) s6 sot-23 0898 0.90 ?1.45 (0.035 ?0.057) 0.90 ?1.30 (0.035 ?0.051) 0.00 ?0.15 (0.00 ?0.006) 0.09 ?0.20 (0.004 ?0.008) (note 2) 2.6 ?3.0 (0.110 ?0.118) note: 1. dimensions are in millimeters 2. dimensions are inclusive of plating 3. dimensions are exclusive of mold flash and metal burr 4. mold flash shall not exceed 0.254mm 5. package eiaj reference is sc-74a (eiaj) 0.95 (0.037) ref 2.80 ?3.00 (0.110 ?0.118) (note 3) 1.90 (0.074) ref
lt1806/lt1807 22 ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660) dimensions in inches (millimeters) unless otherwise noted. u package descriptio msop (ms8) 1100 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" (0.152mm) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.043 (1.10) max 0.009 ?0.015 (0.22 ?0.38) 0.005 0.002 (0.13 0.05) 0.034 (0.86) ref 0.0256 (0.65) bsc 12 3 4 0.193 0.006 (4.90 0.15) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102)
lt1806/lt1807 23 dimensions in inches (millimeters) unless otherwise noted. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
lt1806/lt1807 24 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2000 18067f lt/lcg 1200 4k ? printed in usa part number description comments lt1395 400mhz current feedback amplifier 800v/ m s slew rate, shutdown lt1399 triple 300mhz current feedback amplifier 0.1db gain flatness to 150mhz, shutdown lt1632/lt1633 dual/quad 45mhz, 45v/ m s rail-to-rail input and output amplifiers high dc accuracy 1.35mv v os(max) , 70ma output current, max supply current 5.2ma/amp lt1809/lt1810 single/dual 180mhz input and output rail-to-rail amplifiers 350v/ m s slew rate, shutdown, low distortion C 90dbc at 5mhz typical applicatio u related parts fet input, fast, high gain photodiode amplifier figure 10 shows a fast, high gain transimpedance ampli- fier applied to a photodiode. a jfet buffer is used for its extremely low input bias current and high speed. the lt1097 and 2n3904 keep the jfet biased at i dss for zero offset and lowest voltage noise. the jfet then drives the lt1806, with r f closing the high speed loop back to the jfet input and setting the transimpedance gain. c4 helps improve the phase margin of the fast loop. output voltage noise density was measured as 9nv/ ? hz with r f short circuited. with r f varied from 100k to 1m, total output noise was below 1mv rms measured over a 10mhz bandwidth. table 4 shows results achieved with various values of r f and figure 11 shows the time domain response with r f = 499k. table 4. results achieved for various r f , 1.2v output step 10% to 90% C3db r f rise time bandwidth 100k 64ns 6.8mhz 200k 94ns 4.6mhz 499k 154ns 3mhz 1m 263ns 1.8mhz + r3 10k r1 10m siemens/ infineon sfh213fa photodiode r2 1m r f 49.9 50 18067 f10 r5 33 r4 2.4k 3 6 4 7 v s + v s v s 2 c2 2200pf c3 0.1 f c1 100pf c4 3pf lt1097 + 2 6 4 7 v out * 2n5486 v s + v s + v s v s 3 lt1806 2n3904 *adjust parasitic capacitance at r f for desired response characteristics v s = 5v figure 10. fast, high gain photodiode amplifier 100mv/div 200ns/div 18067 f11 figure 11. step response with r f = 499k

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